Reboot of VHDL support in Verilator

Introduction

Verilator is a free/libre HDL simulator with main purpose of doing fast simulations. Verilator compiles a Verilog design into an executable C++ model. The stimuli are then applied using C++ or SystemC. To reach the performance goal, some approximations are made. Verilator is only used for RTL simulations as it can only evaluate the design state on signal edges. No delays can be taken into account. Only 0/1 values are supported, no X or Z.

For some time, I have been trying to add VHDL (at least 93) to Verilator. I tried a lot of different options for the frontend. I first tried to use the Bison parser generator with a grammar found on the internet, but it was full of Shift/Reduce conflits which were quite hard to debug.

I then tried to use Antlr4 and it was more promising but more work was to go. Antlr was only supporting C# and Java runtimes at the time. So I put that away.

Using NVC

Then, using NVC, Nick’s VHDL compiler was the easiest way to go. NVC already provides a full compiler frontend for VHDL 2008 parsing. I just added an Abstract Syntax Tree export (AST) JSON dump to be importer by Verilator.

At the output, I expect to see a well formed AST in a JSON format.

Importing in Verilator

As I use Verilator as a driver, the tiny process library is used to launch NVC and collect the result, stdout and stderr. This result is read back using rapidJSON library which then recreates the AST in Verilator with SystemVerilog equivalent of the VHDL constructs.

Translation Hypothesis

Currently, only one entity/architecture pair is translated as a module. If more architectures are added, Verilator is likely to fail silently.

The NVC Ast shall hopefully remain stable in a forseeable future. NVC is supposed to catch all the errors user can make.

Elaboration is done by Verilator, not NVC. In this case, full mixed HDL support is possible.

Components are not translated, if it looks for a component instanciation, it would have the same name as the entity, therefore, only entity translation is required.

Verilator has now a simple PWM core as simple working VHDL example.